library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.NUMERIC_STD.all;

entity uc is
	port(
		instruccion	: in	std_logic_vector(31 downto 26);
		regDst		: out	std_logic;
		aluSrc		: out	std_logic;
		memToReg	: out	std_logic;
		regWrite	: out	std_logic;
		memRead		: out	std_logic;
		memWrite	: out	std_logic;
		branch		: out	std_logic;
		aluOp		: out	std_logic_vector(1 downto 0)
	);
end uc;

architecture uc_arch of uc is

begin

	process(instruccion) begin
	
		case instruccion is
			-- R-type
			when "000000" =>
				regDst		<= '1';
				aluSrc		<= '0';
				memToReg	<= '0';
				regWrite	<= '1';
				memRead		<= '0';
				memWrite	<= '0';
				branch		<= '0';
				aluOp		<= "10";
			-- LW
			when "100011" =>
				regDst		<= '0';
				aluSrc		<= '1';
				memToReg	<= '1';
				regWrite	<= '1';
				memRead		<= '1';
				memWrite	<= '0';
				branch		<= '0';
				aluOp		<= "00";
			-- SW
			when "101011" =>
				regDst		<= '0'; -- X
				aluSrc		<= '1';
				memToReg	<= '0'; -- X
				regWrite	<= '0';
				memRead		<= '0';
				memWrite	<= '1';
				branch		<= '0';
				aluOp		<= "00";
			-- BEQ
			when "000100" =>
				regDst		<= '0'; -- X
				aluSrc		<= '0';
				memToReg	<= '0'; -- X
				regWrite	<= '0';
				memRead		<= '0';
				memWrite	<= '0';
				branch		<= '1';
				aluOp		<= "01";
			-- LUI
			when "001111" =>
				regDst		<= '0';
				aluSrc		<= '1';
				memToReg	<= '0';
				regWrite	<= '1';
				memRead		<= '0';
				memWrite	<= '0';
				branch		<= '0';
				aluOp		<= "11";
			when others =>
				regDst		<= '0';
				aluSrc		<= '0';
				memToReg	<= '0';
				regWrite	<= '0';
				memRead		<= '0';
				memWrite	<= '0';
				branch		<= '0';
				aluOp		<= "00";
		end case;

	end process;

end uc_arch;
